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US 2019/0317773 A1Published application
Collaborative processor and system performance and power management
AssigneeIntel Corporation
InventorsGuy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
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Abstract
The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
Claims20
A processor comprising:
- circuitry to read platform power management interface registers;
- and
- a power control unit (PCU) communicatively coupled to the platform power management interface registers, and wherein the PCU is to provide a requested performance according to the platform power management interface registers read by the circuitry.
A system comprising:
- a hardware platform interface to communicate with an operating system (OS), wherein the OS is to read platform power management interface registers;
- and
- a processor communicatively coupled to the hardware platform interface, wherein the processor includes:
- circuitry to read platform power management interface registers;
- and
- a power control unit (PCU) communicatively coupled to the platform power management interface registers, and wherein the PCU is to provide a requested performance according to the platform power management interface registers read by the circuitry.
3 more elements
An apparatus comprising:
- first circuitry to read one or more platform power management interface registers to determine a range of available performance values;
- second circuitry to select a plurality of performance values, wherein a platform is inhibited from variation of a delivered performance above or below a selected performance level when selected;
- and
- third circuitry to evaluate platform performance for the plurality of selected performance values.
1 more element
Dependencies are inferred from the claim text.