Systems and methods for stream-dataflow acceleration
AssigneeSimpleMachines Inc.
InventorsKarthikeyan Sankaralingam, Anthony Nowatzki, Vinay Gangadhar, Preyas Shah, Newsha Ardalani
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Abstract
According to some embodiments, a dataflow accelerator comprises a control/command core, a scratchpad and a coarse grain reconfigurable array (CGRA). The scratchpad comprises a write controller to transmit data to an input vector port interface and to receive data from the input vector port interface. The CGRA receives data from the input vector port interface where the CGRA comprising a plurality of interconnects and a plurality of functional units.
Claims20
A dataflow accelerator, comprising:
- a control core;
- a plurality of stream engines to receive commands from the control core;
- and
- a coarse grain reconfigurable array (CGRA) to receive data from the plurality of stream engines.
A method of flow control through a coarse grain reconfigurable array (CGRA), the method comprising:
- receiving data from a plurality of stream engines at a CGRA including a plurality of interconnects and a plurality of functional units;
- delaying the received data to control flow through the CGRA;
- processing the data via the functional units;
- and
- outputting a result to a plurality of output vector ports.
A non-transitory computer-readable medium comprising processor executable instructions that when executed by a processor perform a method of flow control through a coarse grain reconfigurable array (CGRA), the method comprising:
- receiving data from a plurality of stream engines at a CGRA including a plurality of interconnects and a plurality of functional units;
- delaying the received data to control flow through the CGRA;
- processing the data via the functional units;
- and
- outputting a result to a plurality of output vector ports.
Dependencies are inferred from the claim text.