US 2019/0317769 A1 · ACCURATE EARLY BRANCH PREDICTION IN HIGH-PERFORMANCE MICROPROCESSORS

Abstract

Branch prediction techniques are described that can improve the performance of pipelined microprocessors. A microprocessor with a hierarchical branch prediction structure is presented. The hierarchy of branch predictors includes: a multi-cycle predictor that provides very accurate branch predictions, but with a latency of multiple cycles; a small and simple branch predictor that can provide branch predictions for a sub-set of instructions with zero-cycle latency; and a fast, intermediate level branch predictor that provides relatively accurate branch prediction, while still having a low, but non-zero instruction prediction latency of only one cycle, for example. To improve operation, the higher accuracy, higher latency branch direction predictor and the fast, lower latency branch direction predictor can share a common target predictor.

Claims20

Dependent claims

A microprocessor, comprising:

a fetch stage configured to retrieve instructions from a memory;
a buffer configured to store instructions retrieved by the fetch stage;
one or more pipelined stages configured to execute instructions stored in the buffer;
and
a predictor, including:
a target predictor connected to the fetch stage and configured to predict branch/target pairs for instructions stored in the buffer;
a first direction predictor connected to the target predictor and configured to predict with a first accuracy a first branch path for each of the branch/target pairs and provide the fetch stage the predicted first branch paths with a latency of a first number of cycle;
and
a second direction predictor connected to the target predictor and configured to predict a second branch path with a second accuracy lower than the first accuracy for each of the branch/target pairs and provide the fetch stage the predicted second branch paths with a latency of a second number of cycles, where the second number of cycles is smaller than the first number of cycles.

6 more elements

A microprocessor, comprising:

a pipelined computing structure, including:
a fetch stage configured to fetch instructions from a memory;
a buffer configured to store instructions fetched by the fetch stage;
and
one or more subsequent stages configured to execute instructions stored in the buffer;
and
a hierarchical branch predictor configured to predict branch paths taken for instructions stored in the buffer and provide the fetch stage the predicted branch paths, the hierarchical branch predictor including:
a zero-cycle branch predictor configured to predict branch paths of instructions stored in the buffer for a sub-set of instructions with a latency of zero pipeline cycles;
a first branch predictor configured to predict branch paths of instructions stored in the buffer with a latency of a plurality of pipeline cycles;
and
a second branch predictor configured to predict branch paths of instructions stored in the buffer having a branch prediction accuracy intermediate to the zero-cycle branch predictor and the first branch predictor with a non-zero latency of a lower number of pipeline cycles than the first branch predictor.

8 more elements

Dependencies are inferred from the claim text.

Accurate early branch prediction in high-performance microprocessors

Life of this patent

Accurate early branch prediction in high-performance microprocessors

Life of this patent

Abstract

Claims20