Convolution Operation Chip And Communications Device

A communications device, comprising a central processing unit (CPU), a double data rate synchronous dynamic random access memory (DDR SDRAM), and a convolution operation chip that are communicatively connected,

• wherein the communication device comprising:
• a data cache circuit, an M×N multiplication accumulator array, and an output control circuit, wherein
• the data cache circuit is configured to transmit a plurality of pieces of convolutional data and a plurality of convolutional parameters used for a convolution operation to a first multiplication accumulation window in the M×N multiplication accumulator array, wherein the plurality of convolutional parameters are determined by the data cache circuit based on a first convolutional parameter matrix, the plurality of pieces of convolutional data are determined by the data cache circuit based on a first convolutional data matrix, the first convolutional parameter matrix comprises A rows and B columns, the first convolutional data matrix comprises D rows and E columns, the first multiplication accumulation window comprises A rows and C columns, A is an integer greater than or equal to 2, B and C are each an integer greater than or equal to 1, D is a positive integer greater than or equal to A, E is an integer greater than or equal to max (B, C), M is a positive integer greater than or equal to A, and N is a positive integer greater than or equal to C;
• the first multiplication accumulation window comprises A×C processing elements, wherein a processing element in an ith row and a jth column is marked as PEi,j, i is set to an integer each time in ascending order of 1 to A in sequence, and corresponding to each value of i, j is set to an integer each time in ascending order of 1 to C in sequence;
• a processing element PEX,Y of the first multiplication accumulation window is configured to perform a multiplication operation on convolutional data of the PEX,Y and a convolutional parameter of the PEX,Y;
• and when C is greater than or equal to 2, the processing element PEX,Y is further configured to:
• transmit the convolutional parameter of the PEX,Y to a PEX,Y+1, transmit the convolutional data of the PEX,Y to a PEX−1,Y+1, and respectively use the convolutional parameter of the PEX,Y and the convolutional data of the PEX,Y as multipliers of multiplication operations performed by the PEX,Y+1 and the PEX−1,Y+1, wherein X is an integer greater than or equal to 2 and less than or equal to A, Y is an integer greater than or equal to 1 and less than or equal to C−1, the convolutional data of the PEX,Y is one of the plurality of pieces of convolutional data transmitted by the data cache circuit, and the convolutional parameter of the PEX,Y is one of the plurality of convolutional parameters transmitted by the data cache circuit;
• the first multiplication accumulation window is configured to perform an addition operation on a product obtained after a PEi,J performs a multiplication operation, to obtain a convolutional result, wherein J is an integer greater than or equal to 1 and less than or equal to C;
• and
• the output control circuit is configured to output the convolutional result;
• wherein the CPU is configured to control the communications device to start the convolution operation, and the DDR SDRAM is configured to input the plurality of pieces of convolutional data and the plurality of convolutional parameters to the data cache circuit of the communications device.