Memory device including memory chips and operation method thereof

A memory device comprising:

• a first memory chip suitable for transmitting read data thereof to a first through-chip channel during a calibration operation;
• a second memory chip suitable for transmitting read data thereof to a second through-chip channel during the calibration operation;
• and
• a master chip suitable for instructing the first memory chip and the second memory chip to simultaneously perform a read operation during the calibration operation, and adjusting a data transmission timing skew between the first memory chip and the second memory chip by comparing a phase of the data transmitted to the first through-chip channel with a phase of the data transmitted to the second through-chip channel.

A method of operating a memory device including a master layer, a first memory layer stacked on the master layer, and a second memory layer stacked on the first memory layer, the operating method comprising:

• setting, by the master layer, the first memory layer and the second memory layer to a calibration mode;
• simultaneously writing, by the master layer, data in the first and second memory layers;
• instructing, by the master layer, the first memory layer and the second memory layer to simultaneously read the respective data;
• receiving, by the master layer, the data read from the first memory layer through a first channel, and receiving, by the master layer, the data read from the second memory layer through a second channel;
• comparing, by the master layer, a phase of the data received through the first channel with a phase of the data received through the second channel;
• and
• adjusting, by the master layer, a delay value of a data transmission channel of at least one of the first memory layer and the second memory layer based on a comparison result during the comparing.