Semiconductor device and ufs system

A semiconductor device that performs data transfer with a universal flash storage (UFS) device, the semiconductor device comprising:

• a Central Processing Unit (CPU);
• a transfer control unit;
• a memory that stores a transfer request list describing processing of the data transfer;
• a Run-Stop register that is set a first value indicating the processing is executable or a second value not indicating the processing is executable, and
• a Door bell register that is set a third value instructing the transfer control unit to perform the data transfer according to the transfer request list or a fourth value not instructing the transfer control unit to perform the data transfer according to the transfer request list, the fourth value being set in the Door bell register when the second value is set in the Run-stop register,
• wherein, when the data transfer is performed, the CPU sets the first value in the Run-stop register and sets the third value in the Door bell register, and
• wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the transfer control unit prevents the Run-stop register to be set the first value or the Door bell register to be set the third value instructing to perform a next data transfer until the data transfer is completed.

A UFS system comprising:

• a universal flash storage (UFS) device, and
• a UFS host that controls data transfer with the UFS device,
• wherein the UFS host includes
• a Central Processing Unit (CPU),
• a UFS host controller,
• a Run-Stop register that sets the UFS host controller into a processing possible state, and
• a Door bell register that is set a third value instructing the UFS host controller to perform the data transfer according to the transfer request list or a fourth value not instructing the UFS host controller to perform the data transfer according to the transfer request list, the fourth value being set in the Door bell register when the second value is set in the Run-stop register, and
• wherein, when the data transfer is performed, the CPU sets the first value in the Run-stop register and sets the third value in the Door bell register, and
• wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller prevents the Run-stop register to be set the first value or the Door bell register to be set the third value instructing to perform a next data transfer until the data transfer is completed.