Idle Loop Detection And Control For Processors

Abstract

Systems and method for idle loop detection and control are disclosed. A processor operates in operating modes including an active mode and a disabled mode, and an interconnect bus is coupled between the processor and one or more additional electronic circuits. Logic within the processor is coupled to snoop the interconnect bus, and the logic is programmed to detect a new idle loop based upon repeated instructions on the interconnect bus and to place the processor in the disabled mode based upon execution of the new idle loop, which represents a previously unknown idle loop for the processor. Further, the logic can be programmed to store state data for the processor when the new idle loop is detected, and the logic can also be programmed to place the processor in the active mode based upon detection of a wakeup event for the new idle loop on the interconnect bus.

Dependencies are inferred from the claim text.