Back power protection (bpp) in a system on a chip (soc) with critical signaling scheme

A System on a Chip (SOC) with back power protection (BPP), the SOC comprising:

• a first power management integrated circuit (PMIC);
• an application processor (AP) coupled to the first PMIC, wherein the AP serves as a master processor;
• a second power management integrated circuit (PMIC) different from the first PMIC;
• a baseband processor (BP) coupled to the second PMIC, wherein the BP serves as a communications processor;
• a logical OR function coupled to the baseband processor (BP);
• a first back power protection (BPP) rail for carrying a first back power protection (BPP) supply output from the first PMIC;
• and
• a second back power protection (BPP) rail for carrying a second back power protection (BPP) supply output from the second PMIC, wherein the second BPP rail is a separate rail from the first BPP rail.

An apparatus for implementing back power protection (BPP) in a System on a Chip (SOC), the apparatus comprising:

• means for transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function;
• means for transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function;
• means for generating a composite BPP power based on the first BPP supply output and the second BPP supply output, wherein the means for generating is the logical OR function;
• and
• means for inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

A computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement back power protection (BPP) in a System on a Chip (SOC), the computer executable code comprising:

• instructions for causing a computer to transmit a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function;
• instructions for causing the computer to transmit a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function;
• instructions for causing the computer to use the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output;
• and
• instructions for causing the computer to input the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.