US 2019/0317548 A1Published application

High performance clock domain crossing fifo

AssigneeIntel Corporation

InventorJason Thong

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Abstract

The disclosure relates to clock-crossing elements that may be used to transfer data between different clock domains. The embodiments include dual clock first-in first-out (FIFO) buffers that may employ toggle-based protocols to manage the transference of information regarding the state of the FIFO buffer. The toggle-based protocols may include a feedback-based handshake and bit-sliced toggle lines to prevent errors due to differences between the clock signals in the different clock domains.

Claims20

Dependent claims

A dual clock first-in first-out (FIFO) buffer, comprising:

a FIFO memory;
a read used register in a read clock domain of the FIFO, wherein the read used register stores a number of available words in the FIFO memory;
a write pending register in a write clock domain of the FIFO, wherein the write pending register stores a number of pending updates to the read used register;
a write-domain encoder in the write clock domain of the FIFO, wherein the write-domain encoder generates an update signal based on the number of pending updates;
a clock-crossing synchronizer in the read clock domain of the FIFO that receives the update signal;
a read-domain decoder in the read clock domain of the FIFO that receives the update signal from the clock-crossing synchronizer and provides a decoded update signal to the read used register;
and
a feedback synchronizer in the write clock domain of the FIFO that receives the update signal from the clock-crossing synchronizer in the read clock domain and updates the write pending register.

5 more elements

A non-transitory computer readable media comprising instructions to generate a bitstream comprising a soft intellectual property (IP) block for a programmable logic device, wherein the soft IP block comprises:

a first-in first-out (FIFO) memory;
and
a FIFO controller comprising:
a read used memory synchronized by a read clock of the programmable logic device, wherein the read used memory stores a number of available words in the FIFO memory;
a write pending memory synchronized by a write clock of the programmable logic device, wherein the write pending memory stores a number of pending updates to the read used memory;
a write-domain toggle encoder synchronized by the write clock, wherein the write-domain toggle encoder generates a toggle-encoded signal based on the number of pending updates;
a clock-crossing synchronizer synchronized by the read clock that receives the toggle-encoded signal;
and
a read-domain toggle decoder synchronized by the read clock that generates an update signal based on the toggle-encoded signal received from the clock-crossing synchronizer and provides a decoded signal to the read used memory, wherein the write-domain toggle encoder and the read-domain toggle decoder are coupled by a plurality of 1-bit lines via the clock-crossing synchronizer, and wherein the toggle-encoded signal comprises a bit-sliced signal.

6 more elements

A system comprising an electronic device that comprises a first clock domain, a second clock domain, and a dual-clock first-in first-out (FIFO) buffer controller, comprising:

a read used register in the first clock domain of the FIFO, wherein the read used register stores a number of available words in a FIFO memory;
a write pending register in the second clock domain of the FIFO, wherein the write pending register stores a first a number of pending updates to the read used register;
a write-domain encoder in the second clock domain of the FIFO, wherein the write-domain encoder generates a first update signal based on the first number of pending updates;
a first clock-crossing synchronizer in the first clock domain of the FIFO that receives the first update signal;
a read-domain decoder in the first clock domain of the FIFO that receives the first update signal from the first clock-crossing synchronizer and provides a first decoded update signal to the read used register;
and
a first feedback synchronizer in the second clock domain of the FIFO that receives the first update signal from the first clock-crossing synchronizer in the first clock domain and updates the write pending register.
a write used register in the second clock domain of the FIFO, wherein the write used register stores a number of words in the FIFO memory;
a read pending register in the first clock domain of the FIFO, wherein the read pending register stores a second number of pending updates to the write used register;
a read-domain encoder in the first clock domain of the FIFO, wherein the read-domain encoder generates a second update signal based on the second number of pending updates;
a second clock-crossing synchronizer in the second clock domain of the FIFO that receives the second update signal;
a write-domain decoder in the second clock domain of the FIFO that receives the second update signal from the second clock-crossing synchronizer and provides a second decoded update signal to the write used register;
and
a second feedback synchronizer in the first clock domain of the FIFO that receives the second update signal from the second clock-crossing synchronizer in the second clock domain and updates the read pending register.

11 more elements

Dependencies are inferred from the claim text.

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Abstract