Low power half-vdd generation circuit with high driving capability

An electronic circuit comprising:

• a common mode reference circuit including:
• a divider stage including:
• a first transistor pair connected in series to a high supply voltage rail;
• a second transistor pair connected in series to the first transistor pair and a low supply voltage rail;
• a third transistor pair connected in series to the high supply voltage rail;
• and
• a fourth transistor pair connected in series to the third transistor pair and the low supply voltage rail;
• and
• a push-pull output stage connected to the divider stage and including:
• a first output stage leg coupled to the high supply voltage rail and the low supply voltage rail, the first output stage leg including a first field effect transistor (FET) and a second FET;
• a second output stage leg coupled to the high supply voltage rail and the low supply voltage rail, the second output stage leg including a third FET connected as a current mirror to a transistor of the third transistor pair, and a fourth FET connected as a current mirror to a transistor of the fourth transistor pair and connected in series with the third FET;
• and
• a common mode reference output connected to a source region or drain region of each of the first, second, third, and fourth FETs.

An electronic circuit comprising:

• a common mode reference circuit including:
• a divider stage including:
• a first n-channel field effect transistor and p-channel field effect transistor (NFET/PFET) pair connected in series to a high supply voltage rail;
• and
• a second NFET/PFET pair connected in series to the first NFET/PFET pair and a low supply voltage rail;
• and
• an output stage including:
• a first FET connected as a current mirror to a transistor of the first NFET/PFET pair;
• a second FET connected as a current mirror to a transistor of the second NFET/PFET pair;
• and
• a common mode reference output at a series connection from the first FET to the second FET;
• and
• a resistive circuit element coupled between a drain region of the PFET of one of the first or second NFET/PFET pair and a gate region of one of the first or second FET of the output stage;
• and
• a capacitor coupled to the resistive circuit element and coupled between the gate region of the first or second FET of the output stage and the series connection from the first FET to the second FET.