Coreless package architecture for multi-chip opto-electronics

An optoelectronic apparatus comprising:

• a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field;
• one or more integrated circuits (ICs) disposed on the first side of the substrate within the BGA field that thermally interface with a printed circuit board (PCB), to which the package is to be coupled;
• and
• one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.

An interconnect structure for coupling an electrical IC to an optical IC, comprising:

• a substrate with a first side and a second side opposite the first side, the substrate comprising:
• a vertical interconnect structure, the interconnect structure comprising:
• multiple metal layers, each metal layer comprising an anode portion at a center, and an extended cathode portion that surrounds the anode,
• wherein between the anode portion and the extended cathode portion at each layer there is a void having a defined thickness;
• and
• a defined number and arrangement of interlayer vias, to fine tune a high-frequency performance of the interconnect structure.

A method of manufacturing an integrated circuit (IC) package, comprising:

• providing a substrate with a first side and a second side opposite the first side;
• providing a ball grid array (BGA) field on the first side of the substrate;
• disposing one or more electrical integrated circuits (ICs) on the first side of the substrate inside the BGA field to thermally interface with a printed circuit board (PCB) to which the package is to be coupled;
• and
• disposing one or more optical ICs coupled to the second side of the substrate and communicatively coupled with the one or more electrical ICs disposed on the first side of the substrate via interconnects provided in the substrate.