Digital tests with radiation induced upsets
AssigneeNXP USA, Inc.
InventorsDANIEL JOSEPH BODOH, Kent Bradley Erington
Life of this patent
Estimating the term…
Abstract
Digital testing is performed on an integrated circuit while radiation upsets are induced at locations of the integrated circuit. For each digital test, a determination is made as to whether there is a variation in the output of the digital test from an expected output of the digital test. If there is variation, a time of the variation is indicated. In one example, a location of a defect in the digital circuit can be determined from the times of the variations. In other embodiments, a mapping of the digital circuit can be made from the times.
Claims22
A method for performing digital testing, the method comprising:
- performing with a test system, a plurality of digital tests on a digital circuit of an integrated circuit where each digital test is performed with a radiation beam focused at a different location of a plurality of locations of the integrated circuit at a specific test time of the digital test, wherein during each digital test of the plurality, the radiation beam is at a setting capable of upsetting a logic state of the digital circuit;
- for each digital test of the plurality, determining with the test system, whether there is a variation in a logic state of an output of the digital circuit from an expected failing digital test output of the integrated circuit and if there is a variation, determining a time of an occurrence of the variation with respect to the specific test time.
A method for performing digital testing, the method comprising:
- performing with a test system, a plurality of scan chain tests on a scan chain of an integrated circuit where each scan chain test is performed with a radiation beam focused at different location of a plurality of locations of the integrated circuit at a specific test time of the scan chain test, wherein during each scan chain test of the plurality, the radiation beam is at a setting capable of upsetting a logic state of the scan chain;
- for each scan chain test of the plurality, determining with the test system, whether there is a variation in a logic state of an output of the scan chain test from an expected scan chain test output of the integrated circuit and if there is a variation, determining a time of an occurrence of the variation with respect to the specific test time;
- wherein the scan chain includes plurality of latches in a scan chain order, the method further comprising providing an indication of the scan chain order of the plurality of latches of the scan chain from the determining a time.
Dependencies are inferred from the claim text.