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US 2019/0313938 A1Published application
Circuit for meeting setup and hold times of a control signal with respect to a clock
AssigneeTexas Instruments Incorporated
InventorRobert Callaghan TAFT
Life of this patent
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Abstract
A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.
Claims4
A circuit, comprising:
- a plurality of series-coupled delay buffers;
- a plurality of logic gates, each logic gate including first and second inputs, the first input of each logic gate is coupled to a corresponding one of the delay buffers;
- and
- a plurality of flip-flops, each flip-flop including a data input and a data output, the data input coupled to an output of a corresponding one of the logic gates and the data output coupled to the second input of one of the corresponding logic gates.
1 more element
Dependencies are inferred from the claim text.