Pll circuit
AssigneeMitsubishi Electric Corporation
InventorsYuki YANAGIHARA, Koji TSUTSUMI, Mitsuhiro SHIMOZAWA
Life of this patent
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Abstract
A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.
Claims5
A PLL circuit comprising:
- a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;
- a frequency divider to perform frequency dividing on an output of the voltage-controlled oscillator;
- a phase frequency comparator to compare an output of the frequency divider with a reference signal;
- a first charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator;
- a loop filter to supply a signal obtained by smoothing the output signal of the first charge pump to the voltage-controlled oscillator;
- a lock detector to detect a locked state and an unlocked state from an output of the phase frequency comparator;
- a counter to be reset when an output of the lock detector switches from the locked state to the unlocked state, and to count the reference signal while the unlocked state is being detected;
- a D/A converter to generate a signal to be added to an output of the loop filter;
- a switch to switch whether to supply an output signal of the D/A converter;
- and
- a parameter controlling circuit to acquire a count value of the counter, and control switching on and off of the switch and an output voltage of the D/A converter so that the count value of the counter is restricted within a set value.
A PLL circuit comprising:
- a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;
- a frequency divider to perform frequency dividing on an output of the voltage-controlled oscillator;
- a phase frequency comparator to compare an output of the frequency divider with a reference signal;
- a first charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator;
- a loop filter to supply a signal obtained by smoothing the output signal of the first charge pump to the voltage-controlled oscillator;
- an OR gate to perform an OR operation, using inputs of an up signal and a down signal of the phase frequency comparator;
- a low-pass filter to pass a pulse having a greater width than a pulse width set value in an output of the OR gate;
- a counter to count an output pulse of the low-pass filter, a count value of the counter being reset when a change in an output frequency of the PLL circuit is equal to or greater than a threshold value;
- a D/A converter to generate a signal to be added to an output of the loop filter;
- a switch to switch whether to supply an output signal of the D/A converter;
- and
- a parameter controlling circuit to acquire a count value of the counter, and control switching on and off of the switch and an output voltage of the D/A converter so that the count value of the counter is restricted within a counter set value.
Dependencies are inferred from the claim text.