Low-power flip flop circuit

A method of operating a flip-flop circuit, comprising:

• in response to a clock signal, the first and second latch circuits are complementarily activated first and second latch circuits so as to latch an input signal to an output signal, and wherein the first and second latch circuits each comprises at most two transistors configured to receive the clock signal, wherein the first latch circuit includes a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the second latch circuit includes a pair of cross-coupled AND-OR-Inverter (AOI) logic gates;
• and
• delaying the clock signal to the first latch circuit, but not delaying the clock signal to the second latch circuit.