US 2019/0296080 A1Published application

Memory device and method for manufacturing the same

AssigneeToshiba Memory Corporation

InventorTadashi IGUCHI

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Abstract

A memory device according to an embodiment includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer parallel to a first direction and a second direction perpendicular to the first direction, and stacked in a third direction perpendicular to the first direction; a first, electrode connected to the first conductive layer; a second electrode connected to the second conductive layer; a third electrode connected to the third conductive layer; and a fourth electrode connected to the fourth conductive layer. The third conductive layer and the fourth conductive layer are not provided between the first electrode and the second electrode. The fourth conductive layer is not provided between the second electrode and the third electrode. A region without the second conductive layer is provided between the second electrode and the third electrode.

Claims11

Dependent claims

A memory device comprising:

a first conductive layer parallel to a first direction and a second direction perpendicular to the first direction;
a second conductive layer parallel to the first conductive layer, the second conductive layer being located in
a third direction perpendicular to the first direction and the second direction with respect to the first conductive layer;
a third conductive layer parallel to the first conductive layer, the third conductive layer being located in the third direction with respect to the second conductive layer;
a fourth conductive layer parallel to the first conductive layer, the fourth conductive layer being located in the third direction with respect to the third conductive layer;
a first electrode extending in the third direction, the first electrode being connected to the first conductive layer;
a second electrode extending in the third direction, the second electrode being connected to the second conductive layer;
a third electrode extending in the third direction, the third electrode being connected to the third conductive layer, the second electrode being located between the first electrode and the third electrode;
and
a fourth electrode extending in the third direction, the fourth electrode being connected to the fourth conductive layer, the third electrode being located between the second electrode and the fourth electrode,
wherein the third conductive layer and the fourth conductive layer are not provided between the first electrode and the second electrode,
the fourth conductive layer is not provided between the second electrode and the third electrode, and
a region without the second conductive layer is provided between the second electrode and the third electrode.

10 more elements

A method for manufacturing a memory device, the method comprising:

stacking a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer with first insulating layers interposed therebetween;
forming a first mask member having an opening portion on the fourth conductive layer;
forming a second mask member covering a first region in the opening portion, the second mask member exposing a second region and a third region in the opening portion on both sides of the first region;
removing the fourth conductive layer using the first mask member and the second mask member as a mask;
removing the second mask member;
forming a third mask member covering a portion above the third conductive layer in the third region, the third mask member exposing a portion above the third conductive layer in the second region and a portion above the fourth conductive layer in the first region;
removing the fourth conductive layer and the third conductive layer, or the third conductive layer and the second conductive layer using the third mask member as a mask;
removing the third mask member;
removing the first mask member;
forming a second insulating layer on the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer;
forming a first contact hole reaching the first conductive layer, a second contact hole reaching the second conductive layer, a third contact hole reaching the third conductive layer, and a fourth contact hole reaching the fourth conductive layer in the second insulating layer;
filling the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole to form a first electrode, a second electrode, a third electrode, and a fourth electrode.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/137,251Filed 20 Sep 2018
Priority: JP 2018-05364021 Mar 2018
Published: 26 Sep 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions
H10B 63/845
Arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays: the switching components being connected to a common vertical conductor
H10N 70/011
Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching: manufacture or…
H10N 70/826
Device geometry: adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Family

US 10,515,997 B2Related patent
US 2019/0296080 A1This patent

From the US filing history. Foreign family members aren’t listed.

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