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US 2019/0296027 A1Published application
Semiconductor devices and methods for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorChangseop Yoon
Life of this patent
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Abstract
A semiconductor device includes a substrate including first and second active patterns thereon, a first gate electrode intersecting the first and second active patterns, first and second source/drain regions on the first and second active patterns, respectively, at one side of the first gate electrode, and an active contact on the first source/drain region so as to be electrically connected to the first source/drain region. The active contact includes a first sub-contact and a second sub-contact. The second sub-contact includes a vertical extension vertically extending toward the substrate. A bottom surface of the vertical extension is lower than a bottom surface of the first sub-contact.
Claims20
A semiconductor device comprising:
- a substrate;
- a device isolation layer disposed on the substrate to define active patterns, the active patterns extending in a first direction and including upper portions protruding upwardly with respect to a top surface of the device isolation layer;
- a gate electrode on the upper portions of the active patterns, the gate electrode extending in a second direction intersecting the first direction;
- a first source/drain region disposed on the upper portion of a first one of the active patterns at one side of the gate electrode;
- and
- an active contact on the first source/drain region and electrically connected to the first source/drain region,
- wherein the active contact includes a first portion vertically overlapping with the first source/drain region, and a second portion extending from the first portion toward the device isolation layer,
- wherein the second portion is spaced apart from the device isolation layer and the first source/drain region with an insulating material interposed therebetween, and
- wherein a top surface of the first portion and a top surface of the second portion are coplanar with each other.
6 more elements
A semiconductor device comprising:
- a substrate;
- a device isolation layer disposed on the substrate to define a first active pattern and a second active pattern, the first and second active patterns extending in a first direction and including upper portions protruding upwardly with respect to a top surface of the device isolation layer;
- a gate electrode on the upper portions of the first and second active patterns, the gate electrode extending in a second direction intersecting the first direction;
- first and second source/drain regions disposed on the upper portions of the first and second active patterns, respectively, at one side of the gate electrode;
- and
- an active contact on the first source/drain region,
- wherein the active contact includes a first portion vertically overlapping with the first source/drain region, and a second portion extending from the first portion toward the device isolation layer,
- wherein the second portion is spaced apart from the device isolation layer, and
- wherein a level of a bottom surface of the active contact decreases from the first source/drain region toward the second source/drain region, reaches a lowest level, and then increases.
6 more elements
A semiconductor device comprising:
- a substrate;
- a device isolation layer disposed on the substrate to define active patterns, the active patterns extending in a first direction and including upper portions protruding upwardly with respect to a top surface of the device isolation layer;
- a gate electrode on the upper portions of the active patterns, the gate electrode extending in a second direction intersecting the first direction;
- a first source/drain region disposed on the upper portion of a first one of the active patterns at one side of the gate electrode;
- and
- an active contact on the first source/drain region and electrically connected to the first source/drain region,
- an interlayer insulating layer covering at least a sidewall of the active contact;
- and
- a conductive line on the interlayer insulating layer and electrically connected to the active contact through a via,
- wherein the active contact includes a first portion vertically overlapping with the first source/drain region, and a second portion extending from the first portion toward the device isolation layer,
- wherein a top surface of the interlayer insulating layer, a top surface of the first portion and a top surface of the second portion are coplanar with each other, and
- wherein the via is on the top surface of the second portion, such that the via vertically overlaps with the device isolation layer under the second portion.
9 more elements
Dependencies are inferred from the claim text.