Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In Fabricating Integrated Circuitry

A method used in fabricating integrated circuitry, comprising:

• forming a plurality of rows of pillar openings that are inter-row staggered;
• forming a pillar in individual of the pillar openings, the pillars projecting elevationally outward relative to an upper surface of material in which the pillar openings were formed;
• forming a ring of masking material circumferentially about the individual pillars, the rings forming individual mask openings defined by four immediately-surrounding of the rings that are in immediately-adjacent of the rows and that are intra-row-staggered with and between immediately-adjacent of the pillar openings;
• using the rings and pillars as a mask while etching the material in which the pillar openings were formed through the mask openings to form individual via openings that are intra-row-staggered with and between immediately-adjacent of the pillar openings;
• and
• forming conductive material in the individual via openings directly electrically coupled with an operative circuit component formed in one of four of the pillar openings that immediately-surround the individual via openings.

A method of forming an array of two transistor-one capacitor memory cells, comprising:

• forming columns of sense lines;
• forming rows of elevationally-extending first and second intra-row-alternating field effect transistors individually having an elevationally inner of their source/drain regions electrically coupled to individual of the sense lines, the first and second transistors comprising access lines above the sense lines, individual of the first and second transistors comprising a gate comprising part of individual of the access lines;
• forming a plurality of capacitor openings that individually extend to an elevationally outer source/drain region of the individual first transistors;
• forming a capacitor pillar in individual of the capacitor openings;
• the capacitor pillar comprising a conductive first capacitor node electrically coupled with individual of the elevationally outer source/drain regions of the individual first transistors, a conductive second capacitor node, and a capacitor dielectric material between the first and second capacitor nodes;
• recessing material in which the capacitor openings were formed to result in uppermost portions of the capacitor pillars projecting elevationally outward relative to an upper surface of the material in which the capacitor openings were formed;
• forming a ring of masking material circumferentially about the projecting portions of individual of the capacitor pillars, the rings forming individual mask openings defined by four immediately-surrounding of the rings in immediately-adjacent of the rows and that are intra-row-staggered with and between immediately-intra-row-adjacent of the capacitor openings;
• using the rings and pillars as a mask while etching the material in which the capacitor openings were formed through the mask openings to form individual via openings to individual of elevationally outer source/drain regions of the individual second transistors;
• removing the projecting portions of the capacitor pillars and the rings from being above the material in which the capacitor openings were formed;
• and
• forming conductive material in the individual via openings electrically coupled to the individual elevationally outer source/drain region of the individual second transistors and electrically coupled with one of four immediately-surrounding of the capacitor pillars.