Apparatuses, Multi-Chip Modules and Capacitive Chips
AssigneeMicron Technology, Inc.
InventorFred D. Fishburn
Life of this patent
Estimating the term…
Abstract
Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.
Claims13
1-34. (canceled)
An apparatus, comprising:
- a capacitive chip electrically connected with an integrated circuit chip;
- the capacitive chip comprising capacitive units, and comprising at least four of the capacitive units per square millimeter, the individual capacitive units each comprising:
- layers in a capacitor stack, the layers being alternating electrode layers and dielectric layers;
- the capacitor stack extending across an undulating topography having elevational offsets of from about 30 microns to about 100 microns;
- the electrode layers comprising one or more metals;
- the dielectric layers comprising one or more oxides;
- and
- the capacitor stack comprising at least 10 of the layers.
A multi-chip module, comprising:
- a power distribution component configured to provide a power supply voltage;
- a capacitive chip electrically coupled to the power distribution component and comprising capacitive units;
- an integrated circuit chip electrically coupled to at least one of the capacitive chip and the power distribution component, the integrated circuit chip comprising a controller configured to provide memory commands to a memory;
- and
- wherein individual of the capacitive units of the capacitive chip comprise:
- layers in a capacitor stack, the layers being alternating electrode layers and dielectric layers;
- the capacitor stack extending across an undulating topography;
- the undulating topography comprising trenches having depths within a range of from about 30 microns to about 100 microns and having bottom widths of at least about 1 micrometer;
- the electrode layers comprising one or more metals;
- the dielectric layers comprising one or more oxides;
- and
- the capacitor stack comprising at least 10 of the layers.
Dependencies are inferred from the claim text.