Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsKeiji IKEDA, Chika TANAKA
Life of this patent
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Abstract
A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.
Claims20
A semiconductor memory device comprising:
- a first memory cell that includes a first transistor and a first capacitor;
- a second transistor having a first terminal that is connected to a first terminal of the first memory cell;
- a first bit line that is connected to a second terminal of the first memory cell;
- a second bit line that is connected to a second terminal of the second transistor;
- and
- a controller configured to turn on the first transistor and turn off the second transistor during a write operation on the first memory cell, and to turn on the first transistor and the second transistor during a read operation on the first memory cell.
A semiconductor memory device comprising:
- a first memory cell that includes a first transistor and a first capacitor;
- a second memory cell that includes a second transistor and a second capacitor;
- a third transistor;
- a first bit line that is connected to a first terminal of the first memory cell;
- a second bit line that is connected to a first terminal of the second memory cell and a first terminal of the third transistor;
- and
- a source line that is connected to a second terminal of the first memory cell, a second terminal of the second memory cell, and a second terminal of the third transistor.
A method of controlling a semiconductor memory device including a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, and a second bit line that is connected to a second terminal of the second transistor, said method comprising:
- turning on the first transistor and turning off the second transistor during a write operation on the first memory cell;
- and
- turning on the first transistor and the second transistor during a read operation on the first memory cell.
Dependencies are inferred from the claim text.