Computer system and memory access technology

A processor of a computer system, the processor comprising:

• an instruction queue, configured to:
• cache a first to-be-processed load/store instruction and a second to-be-processed load/store instruction and obtain first dependency information between the first load/store instruction and the second load/store instruction, wherein the first dependency information indicates that an address to be accessed by using the second load/store instruction depends on a value of a first destination register of the first load/store instruction, and the first destination register is configured to store a first load/store result of the first load/store instruction;
• and
• a load/store unit (LSU), configured to send a first load/store request to a memory controller in the computer system based on the first load/store instruction;
• and send a second load/store request to the memory controller based on the second load/store instruction, wherein the second load/store request comprises the first dependency information.

A memory access method, wherein the method is applied to a computer system comprising a processor and a memory controller, and the method comprises:

• obtaining, by the processor, first dependency information between a first to-be-processed load/store instruction and a second to-be-processed load/store instruction, wherein the first dependency information indicates that an address to be accessed by using the second load/store instruction depends on a value of a first destination register of the first load/store instruction, and the first destination register is configured to store a first load/store result of the first load/store instruction;
• sending, by the processor, a first load/store request to the memory controller in the computer system based on the first load/store instruction;
• sending, by the processor, a second load/store request to the memory controller based on the second load/store instruction, wherein the second load/store request comprises the first dependency information;
• accessing, by the memory controller, a memory of the computer system based on the first load/store request, to obtain the first load/store result;
• obtaining, by the memory controller based on the first load/store result and the first dependency information, an address to be accessed by using the second load/store request;
• executing, by the memory controller, the second load/store request based on the address to be accessed by using the second load/store request, to obtain a second load/store result;
• and
• returning, by the memory controller, the first load/store result and the second load/store result to the processor.