Floating-point dot-product hardware with wide multiply-adder tree for machine learning accelerators

A semiconductor apparatus comprising:

• one or more substrates;
• and
• logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
• conduct a first alignment between a plurality of floating-point numbers based on a first subset of exponent bits;
• conduct, at least partially in parallel with the first alignment, a second alignment between the plurality of floating-point numbers based on a second subset of exponent bits, wherein the first subset of exponent bits are least significant bits (LSBs) and the second subset of exponent bits are most significant bits (MSBs);
• and
• add the aligned plurality of floating-point numbers to one another.

A computing system comprising:

• a network controller;
• and
• a processor coupled to the network controller, the processor including logic coupled to one or more substrates to:
• identify individual exponents of a plurality of floating-point numbers;
• identify a maximum exponent across the individual exponents;
• and
• conduct a subtraction of the individual exponents from the maximum exponent, wherein the subtraction is conducted from most significant bit (MSB) to least significant bit (LSB).

A semiconductor apparatus comprising:

• one or more substrates;
• and
• logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
• identify individual exponents of a plurality of floating-point numbers;
• identify a maximum exponent across the individual exponents;
• and
• conduct a subtraction of the individual exponents from the maximum exponent, wherein the subtraction is conducted from most significant bit (MSB) to least significant bit (LSB).