Semiconductor device

A memory system comprising:

• a memory;
• product-sum operation circuitry configured to perform a product-sum operation using first data and second data read from the memory, the first data and the second data each expressed in a matrix form;
• and
• a processor configured to receive a result of the product-sum operation from the product-sum operation circuitry,
• wherein the product-sum operation circuitry comprises a plurality of operation circuits each comprising
• a multiplier including a first input terminal and a second input terminal and configured to calculate a product of a value input via the first input terminal and a value input via the second input terminal, and
• an accumulator configured to integrate an output of the multiplier and output an integrated value that is obtained by integrating output values of the multiplier, and
• wherein the plurality of operation circuits are divided into groups by two manners, where by the first manner multiple operation circuits are configured to receive a common first value as a part of the first data via the respective first input terminals, and by the second manner multiple operation circuits in each of the groups are configured to receive a common second value as a part of the second data via the respective second input terminals.