Semiconductor fabrication design rule loophole checking for design for manufacturability optimization
AssigneeGlobalfoundries, Inc.
InventorsCHIEH-YU LIN, DONGBING SHAO, KEHAN TIAN, ZHENG XU
Life of this patent
Estimating the term…
Loading patent…
AssigneeGlobalfoundries, Inc.
InventorsCHIEH-YU LIN, DONGBING SHAO, KEHAN TIAN, ZHENG XU
Estimating the term…
Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
A system for optimizing fabrication of a wafer, the system comprising:
A computer program product for optimizing fabrication of a wafer, the computer program product comprising a non-transitory computer readable storage medium, the non-transitory computer readable storage medium comprising computer executable instructions, wherein the non-transitory computer readable storage medium comprises instructions to:
A method for optimizing the fabrication of a wafer, the method comprising:
Dependencies are inferred from the claim text.