Semiconductor device, semiconductor designing device, and semiconductor test device

A semiconductor designing device comprising:

• logic synthesis circuitry that generates a design target circuitry by logic synthesis;
• test circuit generator that divides the design target circuitry into a plurality of circuit blocks and incorporates a scan chain circuitry for a scan test into each of the circuit blocks;
• first pattern generator that generates a first test pattern for the scan test in each of the plurality of circuit blocks;
• redundancy judgment circuitry that judges whether the scan test is redundant based on results of the scan test performed with the first test pattern provided to the corresponding circuit block;
• redundancy avoidance circuitry that generates a clock gating circuitry to stop supply of a clock signal to the scan chain circuitry in the circuit block judged as redundant, and generates, in the circuit block including the scan chain circuitry judged as redundant, a bypass path to bypass the scan chain circuitry judged as redundant and a selection circuitry to switch between selection of an output signal from the scan chain circuitry and a signal passing through the bypass path based on an enable signal;
• second pattern generator that generates a second test pattern for a scan test to be provided to the circuit block judged as redundant by the redundancy judgment circuitry;
• and
• layout circuitry that designs layout of the design target circuitry based on results of processing by the logic synthesis circuitry, the test circuit generator, and the redundancy avoidance circuitry.