Unified hardware accelerator for symmetric-key ciphers

A method to perform non-Advanced Encryption Standard (AES) cipher operations, comprising:

• performing a first non-AES affine transformation on a non-AES cipher input vector, wherein the first non-AES affine transformation is a mapping that includes multiplication by a matrix AS1 and a translation that includes addition of a vector bS1;
• passing the input vector after the first non-AES affine transformation to an AES substitution box (S-box) for an AES encryption cipher, wherein the AES S-box performs an inversion followed by an AES affine transformation on input vectors, wherein the AES affine transformation uses a mapping matrix and translation vector as specified by the AES;
• bypassing the AES affine transformation of the AES S-box;
• and,
• performing a second non-AES affine transformation on the input vector after inversion by the AES S-box, wherein the second non-AES affine transformation is a mapping that includes multiplication by a matrix AS2 and a translation that includes addition of a vector bS2

A computer-readable storage medium comprising instructions to cause processing circuitry having an instruction set for Advanced Encryption Standard (AES) cryptographic hardware acceleration, upon execution of the instructions by the processing circuitry, to:

• perform a first non-AES affine transformation on a non-AES cipher input vector, wherein the first non-AES affine transformation is a mapping that includes multiplication by a matrix AS1 and a translation that includes addition of a vector bS1;
• pass the input vector after the first non-AES affine transformation to an AES substitution box (S-box) for an AES encryption cipher, wherein the AES S-box performs an inversion followed by an AES affine transformation on input vectors, wherein the AES affine transformation uses a mapping matrix and translation vector as specified by the AES;
• bypass the AES affine transformation of the AES S-box;
• and, perform a second non-AES affine transformation on the input vector after inversion by the AES S-box, wherein the second non-AES affine transformation is a mapping that includes multiplication by a matrix AS2 and a translation that includes addition of a vector bS2.