Successive approximation register analog-to-digital converter and associated method

A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:

• a digital-to-analog converter (DAC), arranged to generate a transforming voltage according to a digital signal and a reference voltage, wherein the digital signal is generated by a digital signal generating circuit coupled to the DAC;
• a comparing circuit, coupled to the DAC, wherein the comparing circuit is arranged to compare the transforming voltage and an input voltage to generate a comparing result, and further arranged to receive a control signal and an output signal, the control signal and the output signal being received at a same time;
• and
• a logic circuit, coupled to the comparing circuit, wherein the logic circuit executes a logic transforming operation upon the comparing result to generate the output signal to the digital signal generating circuit and the comparing circuit, and the logic circuit does not comprise an AND gate;
• wherein the control signal controls the comparing circuit to enable/disable the SAR ADC.