Device and method for controllably delaying electrical signals

Abstract

In order to prevent or at least reduce parasitic capacitive loads at a device (200) for controllably delaying an electrical signal, the device comprising a first signal transfer path (207) between a signal input (201) and a signal output (204), the first signal transfer path (207) comprising a first signal transfer stage (208) with a first differential pair (209) and a common, adjustable first quiescent current source (212), a second signal transfer path (213) between the signal input (201) and the signal output (204), the second signal transfer path (213) comprising a second signal transfer stage (214) with a second differential pair (215) and a common, adjustable second quiescent current source (218), and an internal delay stage (219), arranged between the signal input (201) and the second signal transfer stage (214) and having a third differential pair (220) and a common, adjustable third quiescent current source (223), and a signal combination stage (224) for additively superimposing the electrical signal transferred via the first signal transfer path (207) on to the electrical signal transferred via the second signal transfer path (213), at least one current modulation stage (235, 236) for adjusting the quiescent current of at least one of the first and/or second and/or third quiescent current source (212, 218, 223) is proposed. A corresponding method for controlling the delay of an electrical signal and for said delaying the electrical signal is also proposed.

Dependencies are inferred from the claim text.