Self-biasing and self-sequencing of depletion-mode transistors
AssigneeMACOM Technology Solutions Holdings, Inc.
InventorsBenone Achiriloaie, Eric Hokenson
Life of this patent
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Abstract
A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.
Claims19
A transistor circuit comprising:
- a transistor having a gate terminal and first and second conduction terminals;
- a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, the first circuit comprising an RF coupler, a rectifier, and a voltage regulator;
- a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage;
- and
- a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage;
- wherein the first circuit, the second circuit, and the switching circuit are configured to apply the gate bias voltage to the gate terminal of the transistor before the first voltage is applied to the first conduction terminal of the transistor.
(canceled)
(canceled)
A method for operating a transistor having a gate terminal and first and second conduction terminals, comprising:
- converting an AC input signal to a gate bias voltage and applying the gate bias voltage to the gate terminal of the transistor using a first circuit comprising an RF coupler, a rectifier, and a voltage regulator;
- converting the AC input signal to a control voltage;
- and
- after applying the gate bias voltage to the gate terminal of the transistor, applying a first voltage to the first conduction terminal of the transistor in response to the control voltage.
(canceled)
A transistor circuit comprising:
- a depletion mode RF power transistor having a gate terminal, a drain terminal and a source terminal;
- a first circuit configured to convert an input RF signal to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, the first circuit comprising an RF coupler, a rectifier, and a voltage regulator;
- a second circuit configured to convert the RF input signal to a control voltage;
- and
- a switching circuit configured to apply a drain voltage to the drain terminal of the transistor in response to the control voltage, wherein the first and second circuits and the switching circuit are configured to apply the gate bias voltage to the gate terminal of the transistor before the drain voltage is applied to the drain terminal of the transistor.
(canceled)
Dependencies are inferred from the claim text.