Close proximity and lateral resistance reduction for bottom source/drain epitaxy in vertical transistor devices

A method of forming a semiconductor structure, the method comprising:

• forming at least one semiconductor fin extending upwards from a semiconductor substrate, wherein a dielectric spacer is present on each sidewall surface of the at least one semiconductor fin and a hard mask is located on a topmost surface of the at least one semiconductor fin;
• recessing the semiconductor substrate to provide a semiconductor pedestal beneath the dielectric spacer and the at least one semiconductor fin:
• performing a self-limiting etch to convert at least the semiconductor pedestal into a semiconductor base comprises an upper portion, a lower portion and a midsection, wherein the midsection has a narrower width than the lower and upper portions;
• forming a bottom source/drain structure on physically exposed surfaces of the semiconductor base and the semiconductor substrate;
• removing each dielectric spacer from length-wise sidewalls of the at least one semiconductor fin;
• forming a gate structure above the bottom source/drain structure and on each side of the at least one semiconductor fin;
• removing the hard mask from the at least one semiconductor fin;
• and
• forming a top source/drain structure on a topmost surface of the at least one semiconductor fin.