Laterally diffused mosfet on fully depleted soi

An apparatus comprising:

• a first semiconductor layer disposed on a first substrate;
• a buried oxide layer disposed on the first semiconductor layer;
• a second semiconductor layer disposed on the buried oxide layer;
• a first gate region, a drain region, and a source region disposed in the second semiconductor layer, wherein the first gate region is positioned between the source and the drain regions;
• a first shallow trench isolation disposed between the drain region at a first end of the second semiconductor layer and the first semiconductor layer;
• and
• a second gate region formed on an etched region on the first semiconductor layer.

A laterally diffused n-type MOSFET device, the device comprising:

• a first gate region configured to be biased by using a positive gate voltage above a predetermined threshold voltage;
• a second gate region disposed on an etched region of a first semiconductor layer between a first shallow trench isolation and a second shallow trench isolation and configured to be biased using the positive gate voltage;
• a source region;
• and
• a drain region,
• wherein:
• the first gate region is configured to operate based on an inversion layer generated by using the positive gate voltage to the first gate region;
• and
• the second gate region is configured to operate based on a back bias generated by using the positive gate voltage to the second gate region.