Laterally diffused field effect transistor and a method of manufacturing the same

A laterally diffused field effect transistor having a gate length direction and a gate width direction, the laterally diffused field effect transistor comprising:

• a first well region having a first conductivity type, said first well region being formed above a substrate having said first conductivity type;
• a drain region having said first conductivity type, said drain region being formed within said first well region and having a first width dimension in said gate width direction, wherein said first well region has a lower concentration of dopant species with said first conductivity type than said drain region;
• a second well region having a second conductivity type that is opposite said first conductivity type, said first well region being formed within said second well region;
• a trench isolation region positioned in said first well region and having a second width dimension in said gate width direction, wherein said trench isolation region is laterally separated from said drain region by a portion of said first well region having said lower concentration of dopant species;
• and
• a source region having said first conductivity type, said source region being formed within said second well region and having a third width dimension in said gate width direction, said third width dimension being greater than said second width dimension and said second width dimension being greater than said first width dimension.

A laterally diffused field effect transistor having a gate length direction and a gate width direction, the laterally diffused field effect transistor comprising:

• a first well region formed above a substrate, said first well region and said substrate having a first conductivity type;
• a plurality of spaced-apart drain regions having said first conductivity type, each of said plurality of spaced-apart drain regions being formed within said first well region and having a first width dimension in said gate width direction;
• a second well region having a second conductivity type that is opposite of said first conductivity type, said first well region being formed within said second well region;
• a source region having said first conductivity type, said source region being formed within said second well region and having a second width dimension in said gate width direction that is greater than said first width dimension;
• a plurality of spaced-apart trench isolation regions positioned in said first well region, each of said plurality of spaced-apart trench isolation regions having a third width dimension in said gate width direction that is less than said second width dimension and greater than said first width dimension, wherein each respective one of said plurality of spaced-apart trench isolation regions is positioned laterally between said source region and a corresponding one of said plurality of spaced-apart drain regions;
• and
• a gate electrode structure positioned above a portion of said first well region, above a portion of said second well region, and above at least a portion of each of said plurality of spaced-apart trench isolation regions.