Igbt devices with 3d backside structures for field stop and reverse conduction

A vertical IGBT device structure, comprising:

• a substrate having a top surface and a bottom surface, the substrate having a first conductivity type;
• a drift region of the first conductivity type formed over the top surface;
• and
• a buffer layer of the first conductivity type formed extending between the drift region and the top surface of the substrate;
• wherein the bottom surface is patterned to have an array of mesas and grooves in the substrate which are placed in alternating fashion so that each mesa is separated from the other by a groove including a groove surface exposing a portion of the buffer layer.

A process for forming vertical IGBT devices, comprising:

• finalizing a front surface process on a front surface of a semiconductor wafer, wherein the front surface process forms a front surface structure;
• and
• forming a backside structure on the semiconductor wafer, including:
• thinning a back surface of the semiconductor wafer down to a predetermined thickness;
• implanting dopants to mesa regions defined on the back surface;
• patterning and etching a back surface of the wafer to form an array of mesas and grooves in the back surface which are formed in alternating fashion so that each mesa is separated from the other by a groove including a groove surface;
• implanting dopants of a first conductivity and a second conductivity to the back surface to form buried regions inside the groove surfaces;
• activating the buried regions and the mesa regions,
• depositing a back metal layer conformally coating the mesas and grooves, and
• filling the grooves between the mesas with solder material.

A process for forming vertical IGBT devices, comprising:

• finalizing a front surface process on a front surface of a semiconductor wafer, wherein the front surface process forms a front surface structure including performing contact etching followed by a contact coating step for coating the contacts with a protection layer including silicon nitride;
• forming a backside structure on the semiconductor wafer, including:
• thinning a back surface of the semiconductor wafer down to a predetermined thickness;
• implanting dopants to mesa regions defined on the back surface;
• patterning and etching a back surface of the wafer to form an array of mesas and grooves in the back surface which are formed in alternating fashion so that each mesa is separated from the other by a groove including a groove surface;
• implanting dopants of a first conductivity and a second conductivity to the back surface to form buried regions inside the groove surfaces;
• activating the buried regions and the mesa regions,
• depositing a back metal layer conformally coating the mesas and grooves, and
• filling the grooves between the mesas with solder material;
• and
• removing the protection layer coating the contacts on the front surface;
• depositing a front side metal;
• and
• passivating the device.