Vertical mos transistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTai-I YANG, Yung-Chih WANG, Shin-Yi YANG, Chih-Wei LU, Hsin-Ping CHEN, Shau-Lin SHUE
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTai-I YANG, Yung-Chih WANG, Shin-Yi YANG, Chih-Wei LU, Hsin-Ping CHEN, Shau-Lin SHUE
Estimating the term…
A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.
A device, comprising:
A device, comprising:
A device, comprising:
Dependencies are inferred from the claim text.