Transistor with source field plates and non-overlapping gate runner layers

A transistor, comprising:

• a semiconductor substrate having a top surface defining a channel region;
• a source contact layer contacting a first end of the channel region;
• a drain contact layer contacting a second end of the channel region;
• a gate layer above the channel region and closer to the source contact layer than the drain contact layer;
• a source field plate extending from the source contact layer along a first dimension of the channel region and over the gate layer;
• a gate runner layer coextending with the source field plate along a second dimension of the channel region perpendicular to the first dimension, the gate runner layer positioned above and away from the gate layer;
• and
• a gate bridge extending from the gate layer, across the source contact layer, and under the gate runner layer, the gate bridge coupled between the gate layer and the gate runner layer.

An integrated circuit, comprising:

• a semiconductor substrate having a top surface;
• and
• transistors, each including:
• a channel region defined on the top surface;
• a source contact layer contacting a first end of the channel region;
• a drain contact layer contacting a second end of the channel region;
• a gate layer above the channel region and closer to the source contact layer than the drain contact layer;
• a source field plate extending above the source contact layer along a first dimension of the channel region and over the gate layer;
• a gate runner layer coextending with the source field plate along a second dimension of the channel region perpendicular to the first dimension, the gate runner layer positioned above and away from the gate layer;
• and
• a gate bridge extending from the gate layer, across the source contact layer, and under the gate runner layer, the gate bridge coupled between the gate layer and the gate runner layer.