High energy ion implantation for junction isolation in silicon carbide devices

A method of manufacturing a semiconductor device, comprising:

• providing a silicon carbide (SiC) epitaxial layer on top of an underlying SiC layer;
• fabricating features of adjacent planar devices in the SiC epitaxial layer, wherein the adjacent planar devices comprise transistors, resistors, capacitors, diodes, or a combination thereof, the SiC epitaxial layer is a first conductive type, and the underlying SiC layer is a second conductive type opposite to the first conductive type;
• forming a junction isolation feature between or around the adjacent planar devices by implanting dopants in the epitaxial SiC layer via high-energy ion implantation, wherein the junction isolation feature has a depth of at least about 2 micrometers (μm) such that the junction isolation feature extends vertically through a thickness of the epitaxial SiC layer and contacts or penetrates into the underlying SiC layer;
• and
• annealing the junction isolation feature.

A silicon carbide (SiC) integrated circuit comprising:

• a SiC layer of a first conductive type;
• a SiC epitaxial layer of a second conductive type disposed on the SiC layer, wherein the second conductive type is opposite to the first conductive type;
• adjacent planar transistors, each comprises a source contact and a drain contact disposed on the SiC epitaxial layer;
• and
• a junction isolation feature formed between or around the adjacent planar transistors, wherein the junction isolation featured is doped with ions of the first conductive type at a concentration that is between about 1×1014 ions per cubic centimeters (ions/cm3) and about 1×1018 ions/cm3, wherein the junction isolation feature has a width that is between about 1 micrometers (μm) and about 10 μm, and wherein the junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer.