Non-volatile memory array and method of manufacturing the same

A non-volatile memory array comprising:

• a plurality of gate structures disposed on a substrate, each of the gate structures including
• a tunneling oxide layer positioned on the substrate,
• a plurality of floating gates positioned on the tunneling oxide layer, each floating gate being arranged along a first direction on the tunneling oxide layer,
• a sidewall gate extending in the first direction and disposed on sidewalls of the plurality of floating gates, and
• a gate dielectric layer interposed between the floating gate and the sidewall gates, the sidewall gates of each gate structure spaced apart from each other;
• a plurality of bit lines disposed over the substrate, each extending in a second direction to intersect the sidewall gate of each of the plurality of gate structures;
• a drain region positioned in an upper surface portion of the substrate, the drain region overlapping one of the bit lines and being electrically connected to the one of the bit lines;
• and
• a source line positioned between each pair of two adjacent sidewall gates, the source line extending in the first direction and being buried in the substrate.