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US 2019/0244964 A1Published application
Embedded SRAM and Methods of Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes.
Claims20
A structure comprising:
- a first fin over a substrate;
- a first gate structure over the first fin;
- a first source/drain region adjacent to the first gate structure;
- a second source/drain region adjacent to the first gate structure, the second source/drain region being on an opposite side of the first gate structure from the first source/drain region;
- a first dislocation plane in the first source/drain region;
- and
- a second dislocation plane in the first source/drain region, the first dislocation plane sloping away from the first gate structure as the first dislocation plane extends from a bottom of the first source/drain region to an upper surface of the first source/drain region, the second dislocation plane sloping toward the first gate structure as the second dislocation plane extends from the bottom of the first source/drain region to the upper surface of the first source/drain region, wherein the first dislocation plane and the second dislocation plane extends parallel to a line perpendicular to a current-flow direction between the first source/drain region and the second source/drain region in a channel region.
4 more elements
A structure comprising:
- a fin over a substrate;
- a first gate structure over the fin;
- a first source/drain region adjacent to the first gate structure;
- a first silicide over the first source/drain region;
- a second source/drain region adjacent to the first gate structure, the second source/drain region being on an opposite side of the first gate structure from the first source/drain region;
- a first dislocation in the first source/drain region;
- and
- a second dislocation in the first source/drain region, wherein the first dislocation and the second dislocation contacts the first silicide, wherein a distance between the first dislocation and the second dislocation increases as the first dislocation and the second dislocation extends away from the first silicide.
5 more elements
A structure comprising:
- a first transistor comprising:
- a first fin extending above a substrate;
- a first gate structure over the first fin;
- a first source/drain region adjacent to the first gate structure, the first source/drain region comprising a first semiconductor material;
- and
- a first dislocation in the first source/drain region;
- and
- a second transistor comprising:
- a second fin extending above the substrate;
- a second gate structure over the second fin;
- and
- a second source/drain region adjacent to the second gate structure, the second source/drain region comprising the first semiconductor material, wherein the second source/drain region are free of dislocations.
9 more elements
Dependencies are inferred from the claim text.