Semiconductor memory device and structure

A semiconductor device, the device comprising:

• a plurality of memory cells;
• and
• peripheral circuits, said peripheral circuits comprise controlling said plurality of memory cells,
• wherein each of said plurality of memory cells comprises a first gate, a second gate, a channel region, at least a first channel facet overlaid by a first charge trap region and a first gate region, and second channel facet overlaid by a second charge trap region and a second gate region,
• wherein a portion of said peripheral circuits are designed to control said first gate and said second gate so to position two distinct memory sites, a first memory site and a second memory site, within said first charge trap region, and
• wherein said first memory site is substantially closer to said first gate than said second memory site.

A semiconductor device, the device comprising:

• a plurality of memory cells;
• and
• peripheral circuits, said peripheral circuits comprise controlling said plurality of memory cells,
• wherein each of said plurality of memory cells comprises a first gate and a second gate,
• wherein said plurality of memory cells each comprise a channel region, at least one channel facet, a charge trap region and a tunneling region,
• wherein a portion of said peripheral circuits are designed to control said first gate and said second gate so to position three distinct memory sites within said charge trap region of said at least one channel facet of at least one of said memory cells.