Suppression of parasitic discharge path in an electrical circuit

4:

• The device of claim 1,
• wherein the protection element comprises a p-n diode,
• wherein a p-type material of the p-n diode is electrically connected to the first power supply node, and
• wherein a n-type material of the p-n diode is electrically connected to the second n-region of the n-p-n parasitic structure.

8:

• The device of claim 7, further comprising:
• a second high-side power supply node;
• and
• a second low-side power supply node positioned between the second high-side power supply node and the input-output node.

10:

• The device of claim 8,
• wherein the first high-side power supply node comprises a first n-well,
• wherein the second high-side power supply node comprises a second n-well that is electrically connected to the first n-well,
• wherein the device further comprises a p-well adjacent to the first n-well, the second n-well, the first low-side power supply node, the second low-side power supply node, and the input-output node,
• and
• wherein a p-region of the n-p-n parasitic structure comprises the p-well.

20:

• A method comprising:
• forming a p-type substrate;
• forming a p-well on the p-type substrate;
• forming an n-well adjacent to the p-well on the p-type substrate;
• forming a first power supply node on the n-well, wherein forming the first power supply node comprises forming p-type material on the n-well;
• forming a second power supply node on the p-well, wherein the second power supply node is positioned between the first power supply node and the input-output node, and wherein forming the second power supply node comprises forming p-type material on the p-well;
• forming an input-output node on the p-well, wherein forming the input-output node comprises forming n-type material on the p-well;
• forming an n-p-n parasitic structure comprising a first n-region and a second n-region, wherein the first n-region comprises the input-output node;
• and
• forming a protection element to block a parasitic flow of positive carriers through the n-p-n parasitic structure from the input-output node to the first power supply node,
• wherein the second n-region is electrically connected to an n-type material of the protection element, and
• wherein the parasitic flow of positive carriers is based on a voltage level of the second power supply node.

21:

• The method of claim 20,
• wherein forming the protection element comprises forming a p-n diode,
• wherein a p-type material of the p-n diode is electrically connected to the first power supply node, and
• wherein a n-type material of the p-n diode is electrically connected to the second n-region of the n-p-n parasitic structure.

23:

• The method of claim 20, wherein the first power supply node is a first high-side power supply node, and wherein the second power supply node is a first low-side power supply node, the method further comprising:
• forming a second high-side power supply node;
• and
• forming a second low-side power supply node positioned between the second high-side power supply node and the input-output node.

24:

• A device comprising:
• a first power supply node;
• an input-output node;
• a second power supply node positioned between the first power supply node and the input-output node;
• and
• a protection element configured to block a parasitic flow of negative carriers through a p-n-p parasitic structure from the input-output node to the first power supply node,
• wherein the parasitic flow of negative carriers is based on a voltage level of the second power supply node,
• wherein a first p-region of the p-n-p parasitic structure comprises the input-output node, and
• wherein a second p-region of the p-n-p parasitic structure is electrically connected to a p-type material of the protection element.

25:

• The device of claim 24,
• wherein the protection element comprises a p-n diode,
• wherein a n-type material of the p-n diode comprises the first power supply node, and
• wherein a p-type material of the p-n diode is electrically connected to the second p-region of the p-n-p parasitic structure.

29:

• The device of claim 28, further comprising:
• a second low-side power supply node;
• and
• a second high-side power supply node positioned between the second low-side power supply node and the input-output node.

31:

• The device of claim 29,
• wherein the first low-side power supply node is adjacent to a first p-well,
• wherein the second low-side power supply node is adjacent to a second p-well,
• wherein the device further comprises a n-well adjacent to the first p-well, the second p-well, the first high-side power supply node, the second high-side power supply node, and the input-output node,
• wherein a second p-region of the p-n-p parasitic structure comprises the first p-well or the second p-well, and
• wherein an n-region of the p-n-p parasitic structure comprises the n-well.