Semiconductor package and manufacturing method thereof

A semiconductor package, comprising:

• a redistribution layer;
• a semiconductor die and a semiconductor device disposed on two opposite surfaces of the redistribution layer, wherein the redistribution layer is electrically connected to the semiconductor die and the semiconductor device;
• a plurality of conductive features electrically connected to the redistribution layer and surrounding the semiconductor die opposite to the semiconductor device;
• a plurality of conductive terminals electrically connected to the redistribution layer and comprising a plurality of first elements surrounding the conductive features and a plurality of second elements disposed on the conductive features and corresponding to the semiconductor die;
• and
• an encapsulant encapsulating the semiconductor die and covering the first elements of the conductive terminals and the conductive features, wherein a portion of the first elements of the conductive terminals is protruded from the encapsulant opposite to the redistribution layer and a portion of the conductive features are exposed by the encapsulant.

A manufacturing method of a package structure, comprising:

• forming a redistribution layer, wherein the redistribution layer comprises a first surface and a second surface;
• disposing a semiconductor die on the second surface of the redistribution layer, wherein the semiconductor die comprises an active surface facing toward the second surface of the redistribution layer;
• forming a plurality of conductive features on the second surface of the redistribution layer, wherein a portion of the conductive features is formed above the semiconductor die;
• forming an encapsulant on the second surface of the redistribution layer to encapsulate the semiconductor die;
• disposing a plurality of semiconductor devices on the first surface of the redistribution layer;
• and
• forming a plurality of conductive terminals on the second surface of the redistribution layer, wherein the conductive terminals comprises a plurality of first elements surrounding the conductive features and a plurality of second elements formed on the conductive features corresponding to the semiconductor die, and a surface of each of the first elements opposite to the encapsulant and a surface of each of the second elements are aligned with a standoff baseline.