Group iii-n transistors for system on chip (soc) architecture integrating power management and radio frequency circuits

A method of integrating high voltage, high power transistors on a substrate, the method comprising:

• forming a plurality of high voltage, high power group III-N field effect transistors on the substrate, the forming further comprising:
• forming a stack of semiconductor material layers on the substrate, the stack comprising a plurality of group III-N semiconductor material layers of differing composition, wherein the substrate comprises crystalline silicon and wherein forming the stack of semiconductor material layers comprises forming a buffer layer comprising GaN and epitaxially growing the stack of semiconductor materials on the buffer layer;
• forming a sacrificial gate structure over at least some of the semiconductor material layers in the stack;
• forming a source and a drain region on opposite sides of the sacrificial gate structure, wherein forming the source and drain regions further comprises epitaxially growing a group III-nitride semiconductor contact layer over exposed regions of the stack of semiconductor material layers, the group III-nitride semiconductor contact layer having a lower bandgap than that of the top barrier layer;
• removing the sacrificial gate structure to expose a surface of the epitaxially grown stack;
• forming a gate dielectric layer on the exposed surface of the epitaxially grown stack with an atomic layer deposition process;
• and
• forming a gate electrode on the gate dielectric layer;
• and
• forming a plurality of silicon-based field effect transistors on the silicon substrate adjacent to the high voltage, high power group III-N field effect transistors.

A system on chip (SoC), comprising:

• forming a power management integrated circuit (PMIC) including at least one of a switching voltage regulator or switching mode DC-DC converter;
• and
• forming an RF integrated circuit (RFIC) including a power amplifier operable to generate a carrier wave frequency of at least 2 GHz, wherein both of the PMIC and RFIC are monolithically integrated onto a same substrate, and wherein at least one of PMIC and RFIC include at least one group III-nitride high electron mobility transistor (HEMT), and wherein the HEMT includes a top barrier layer having a first thickness between a dielectric layer at the bottom of a gate electrode and a channel layer and a second, greater thickness, between a source contact and the channel layer and between a drain contact and the channel layer, and a third thickness between a first dielectric spacer and the channel layer, the first dielectric spacer disposed between the gate electrode and the source contact, and the third thickness between a second dielectric spacer and the channel layer, the second dielectric spacer disposed between the gate electrode and the drain contact, wherein the third thickness is intermediate to the first thickness and the second thickness, and the third thickness comprises a portion of the top barrier layer between 25% and 50% of a thickness of a portion of the top barrier layer beneath the source contact and the drain contact, wherein the first and second dielectric spacers comprise a dielectric material having a lower dielectric constant than a dielectric material of the dielectric layer at the bottom of the gate electrode, wherein the dielectric layer at the bottom of the gate electrode further extends along sidewalls of the gate electrode, the dielectric layer between and in contact with the first dielectric spacer and the gate electrode, and the dielectric layer between and in contact with the second dielectric spacer and the gate electrode, and wherein the first dielectric spacer is not continuous with the second dielectric spacer.