3d semiconductor device and structure

A method to construct a 3D system, the method comprising:

• providing a base wafer;
• and then
• transferring a first memory wafer on top of said base wafer;
• and then
• thinning said first memory wafer;
• and then
• transferring a second memory wafer on top;
• and then
• thinning said second memory wafer;
• and
• transferring a memory control on top;
• and then
• thinning said memory control,
• wherein said first memory wafer comprises a cut-layer, and
• wherein said thinning comprises using said cut-layer to control the thickness of said first memory wafer.

A 3D device, the device comprising:

• a first stratum comprising a first bit-cell array, said first bit-cell array comprises a hundred independent first rows;
• a second stratum comprising a second bit-cell array, said second bit-cell array comprises a hundred independent second rows,
• wherein said second stratum overlays said first stratum;
• and
• at least one hundred vertical bit-lines each connected to a respective one hundred horizontal first bit-lines and one hundred horizontal second bit-lines,
• wherein said hundred horizontal first bit-lines comprise control of said first bit-cell array,
• wherein said hundred horizontal second bit-lines comprise control of said second bit-cell array, and
• wherein each of said hundred vertical bit-lines could be used to control a different one of said hundred independent first rows, or control a different one of said hundred independent second rows.

A 3D device, the device comprising:

• a first stratum of first bit-cell memory arrays;
• a second stratum of second bit-cell memory arrays;
• and
• a third stratum,
• wherein said second stratum overlays said first stratum,
• wherein said third stratum overlays said second stratum,
• wherein said third stratum comprises a plurality of word-line decoders to control said first bit-cell memory arrays and said second bit-cell memory arrays.