Integrated circuit with backside structures to reduce substrate warp

A method of manufacturing an integrated circuit device, comprising:

• providing a semiconductor wafer;
• forming first structures on a first side of the semiconductor wafer, the first structures including deep trench capacitors;
• measuring a first amount of bow of the semiconductor wafer after the first structures have been formed;
• determining a characteristic for one or more stress-inducing films to be formed based on the measured first amount of bow;
• and
• forming the one or more stress-inducing films with the determined characteristic on a second side of the semiconductor wafer and/or on the first side of the semiconductor wafer to reduce the first amount of bow in the semiconductor wafer.

A method of manufacturing an integrated circuit device, comprising:

• providing a first semiconductor wafer;
• forming first structures on a first side of the first semiconductor wafer, the first structures including deep trench capacitors;
• and
• forming stress-inducing second structures on a second side of the first semiconductor wafer, the second side being opposite the first side, wherein forming the stress-inducing second structures on the second side of the first semiconductor wafer includes forming trenches in the first semiconductor wafer and then filling the trenches with stress-inducing material.