Semiconductor packages and display devices including the same

A semiconductor package comprising:

• a film substrate comprising a first bonding region, a chip region, and a second bonding region that are in a sequence in a first direction, and further comprising first and second surfaces that are opposite to each other;
• a first pad group comprising first and second pads that are on the first surface in the chip region and are spaced apart from each other in a second direction that intersects the first direction;
• a second pad group comprising a third pad that is on the first surface in the chip region and is spaced apart in the second direction from the second pad with the first pad therebetween;
• a first semiconductor chip on the first pad group;
• a second semiconductor chip on the second pad group and adjacent the first semiconductor chip in the second direction;
• a first wire comprising a first via that penetrates the film substrate, a first extended portion that connects the first pad and the first via, and a second extended portion that connects the first via and the second bonding region and extends along the second surface of the film substrate;
• a second wire connecting the second pad and the first bonding region;
• and
• a third wire comprising a second via that penetrates the film substrate, a third extended portion that connects the third pad and the second via, and a fourth extended portion that connects the second via and the second bonding region and extends along the second surface of the film substrate.

A semiconductor package comprising:

• a substrate comprising a first bonding region, a second bonding region, and a chip region that is between the first and second bonding regions in a first direction, the substrate further comprising first and second surfaces that are opposite to each other;
• a pad group comprising first and second pads that are on the first surface in the chip region and are spaced apart from each other in a second direction that intersects the first direction, wherein the pad group is adjacent the first bonding region;
• a first semiconductor chip on the pad group on the first surface;
• a second semiconductor chip on the first surface in the chip region, adjacent the first semiconductor chip in the second direction, and closer to the first pad than to the second pad;
• a first wire connecting the first pad and the second bonding region;
• and
• a second wire connecting the second pad and the second bonding region and extending along the first surface of the substrate,
• wherein the first wire comprises a first via that penetrates the substrate, a first extended portion that connects the first pad and the first via, and a second extended portion that connects the first via and the second bonding region and extends along the second surface of the substrate.