Hybrid copper structure for advance interconnect usage

An integrated chip, comprising:

• a dielectric structure arranged over an upper surface of a substrate;
• a plurality of first interconnect structures arranged within the dielectric structure and vertically extending from a first horizontal plane to a second horizontal plane between the substrate and the first horizontal plane;
• a second interconnect structure laterally separating a part of a sidewall of a first one of the plurality of first interconnect structures from a sidewall of the dielectric structure facing the part of the sidewall, wherein the plurality of first interconnect structures and the second interconnect structure comprise one or more different conductive materials;
• and
• wherein the second interconnect structure has a bottom surface that faces the substrate and that is separated from the second horizontal plane by a non-zero distance.

An integrated chip, comprising:

• an inter-level dielectric (ILD) layer disposed over an upper surface of a substrate;
• a first interconnect structure arranged within the ILD layer;
• a second interconnect structure arranged within the ILD layer and comprising a conductive core and a liner separating the conductive core from the ILD layer, wherein the first interconnect structure and the second interconnect structure comprise one or more different conductive materials;
• and
• wherein a horizontal plane that is parallel to the upper surface of the substrate extends through sidewalls of the first interconnect structure and the second interconnect structure.