Fabrication of transistors having stressed channels

A method for producing, on one same plate, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method comprising:

• providing a plate comprising the at least one first transistor and the second transistor;
• forming at least one stressed nitride-based layer, on the at least one first transistor and the second transistor, the stressed nitride-based layer being voltage stressed;
• depositing a protective layer so as to cover a first zone of the stressed nitride-based layer, the first zone covering at least partially the at least one first transistor and leaving a second zone of the stressed nitride-based layer uncovered, the second zone at least partially covering the second transistor;
• and
• modifying a type of stress of the second zone of the stressed nitride-based layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the stressed nitride-based layer is compression stressed.