Semiconductor Device and Method

A method comprising:

• forming a fin extending from a substrate;
• forming a gate stack on a channel region of the fin;
• growing a source/drain region adjacent the channel region of the fin, the source/drain region being Si doped with P impurities;
• growing a semiconductor cap layer on the source/drain region, the semiconductor cap layer being Si doped with Ge impurities;
• forming an inter-layer dielectric (ILD) on the semiconductor cap layer;
• etching an opening in the ILD, the opening exposing a first portion of the semiconductor cap layer, a second portion of the semiconductor cap layer remaining covered by the ILD;
• depositing a first conductive layer on the first portion of the semiconductor cap layer;
• annealing the first conductive layer and the semiconductor cap layer to form a silicide layer on the source/drain region, wherein the annealing is performed until substantially all of the Ge impurities in the first portion of the semiconductor cap layer have segregated to the silicide layer;
• and
• depositing a second conductive material on the silicide layer.

A method comprising:

• forming a gate stack over a substrate;
• growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si;
• growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region being free of the Ge impurities;
• depositing a metal layer over the semiconductor cap layer;
• annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, wherein during the annealing, the Ge impurities in the semiconductor cap layer segregate at grain boundaries of the silicide layer;
• and
• depositing a conductive material over the silicide layer.