Surface-aligned lithographic patterning approaches for back end of line (beol) interconnect fabrication

An integrated circuit structure, comprising:

• a substrate;
• a plurality of alternating first and second conductive lines along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate;
• a conductive via on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via having a flat top surface and outwardly tapered sidewalls, and the conductive via centered over the one of the conductive lines;
• and
• a second ILD layer above the plurality of alternating first and second conductive lines and laterally adjacent to the conductive via, the second ILD layer having an uppermost surface substantially co-planar with the flat top surface of the conductive via.

A method of fabricating a back end of line (BEOL) metallization layer, the method comprising:

• forming a plurality of conductive lines along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above a substrate;
• forming a surface quencher layer on upper surfaces of the ILD layer between adjacent ones of the plurality of conductive lines;
• forming a resist layer on the plurality of conductive lines and on the surface quencher layer on upper surfaces of the ILD layer;
• performing a lithographic exposure of a portion of the resist layer above one of the plurality of conductive lines, wherein the surface quencher layer creates a sensitivity modulated region in the resist layer adjacent to the portion of the resist layer;
• developing the resist layer to remove portions of the resist layer not exposed to the lithographic exposure, to remove the sensitivity modulated region, and to retain the portion of the resist layer;
• and
• forming a conductive via in place of the portion of the resist layer, the conductive via on and electrically coupled to the one of the plurality of conductive lines.

A method of fabricating a back end of line (BEOL) metallization layer, the method comprising:

• forming a plurality of conductive lines along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above a substrate;
• forming a surface quencher layer on an upper surface of one of the plurality of conductive lines;
• forming a resist layer on the plurality of conductive lines and on the surface quencher layer;
• performing a lithographic exposure of portions of the resist layer adjacent to the one of the plurality of conductive lines, wherein the surface quencher layer creates a sensitivity modulated region in the resist layer above the one of the plurality of conductive lines;
• developing the resist layer to remove portions of the resist layer not exposed to the lithographic exposure, to remove the sensitivity modulated region, and to retain the portions of the resist layer;
• and
• forming a conductive via on and electrically coupled to the one of the plurality of conductive lines.