Sense amplifier and latch circuit for a semiconductor memory device and method of operation thereof

A semiconductor memory device, comprising:

• a memory cell;
• a bit line connected to the memory cell;
• a sense amplifier connected to the memory cell through the bit line, wherein the sense amplifier includes a sense node connected to the bit line and a sense transistor having a gate connected to the sense node;
• and
• a control circuit configured to adjust a voltage applied to a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor.

A method of performing a verification operation in a semiconductor device having a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line, wherein the sense amplifier includes a sense node connected to the bit line and a sense transistor having a gate connected to the sense node, said method comprising:

• applying a first voltage to a back gate of the sense transistor;
• and
• applying a second voltage to a source of the sense transistor, wherein
• one of the first and second voltages are adjusted to correct for a variation of a threshold voltage of the sense transistor.